RTL Implementation of MP3 Decoder IP Core

RTL IMPLEMENTATION OF MP3 DECODER IP CORE
Abstraction
The intent of this survey is to look into the effectivity of the MP3 decrypting design in hardware comparison to the more popular package design. Nowadays, the MP3 file format is the most popular criterion for audio compaction, used in playback device such as audio participants and nomadic phones. While MP3 decryption is one of the indispensable portion in multimedia system, most of the decryption design are software-based, peculiarly because of the design of the system, which is easier compared to the hardware portion. However, the package design has higher clock, therefore higher power ingestion. This happens because of the design itself ; it has more iteration in the scheduling algorithm. There are undertakings that combine both hardware and package design in the MP3 decrypting creative activity, but the standalone hardware rational belongings ( IP ) nucleus is still non good explored.

This paper will present a brief position on the basicss of the undertaking, every bit good as the needed inside informations needed in working on the undertaking. Every inside informations presented in the study are either gathered from diaries, books and the online beginning available. The mark of this undertaking is to run the designated IP nucleus and implemented in Register Transfer Level ( RTL ) manner, in which it easy means utilizing the hardware descriptive linguistic communication ( HDL ) as the footing linguistic communication for the design.

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Table OF CONTENTS

Chapter

Title

Page

Dedication

2

Recognitions

3

Abstraction

4

Table OF CONTENTS

5

List OF FIGURES

7

1.0

Introduction

8

1.1

Undertaking Background

8

1.2

Aim

9

1.3

Problem Statement

9

1.4

Scope of the Undertaking

10

2.0

Literature Review

11

2.1

Related Studies and Previous Work

11

2.2

Introduction to the MP3 Decoding Core

13

2.2.1

Synchroscope

14

2.2.2

Huffman Decoding

15

2.2.3

Requantiser

16

2.2.4

Reordering

17

2.2.5

Antialiasing

18

2.2.6

Inverse Modified Discrete Cosine Transform ( IMDCT )

19

2.2.7

Synthesis Polyphase Filterbank

20

3.0

Research Methodology

22

3.1

Introduction

22

3.2

Ocular Representation of Research Methodology

22

3.2.1

Altera DE2 Board

24

3.2.2

Altera Quartus II

25

3.2.3

NIOS II

25

List OF FIGURES

FIGURE NO.

Title

Page

2.1

The MP3 bitstream format

19

2.2

The three parts of frequence line

20

2.3

The reordering procedure ( the darker coloring material represents higher frequences )

22

2.4

The antialias butterfly

23

2.5

Types of window sequences in a subband

25

2.6

The IMDCT operation flow

27

3.1

The undertaking work flow

3.2

The Altera DE2 board ( beginning: hypertext transfer protocol: //www.terasic.com.tw/ )

29

3.3

The Quartus II work bench environment

30

3.4

The NIOS II work bench environment

31

Chapter 1
Introduction

Undertaking Background

MPEG-1/2 audio layer-3 ( MP3 ) is a most popular format for playback of high quality compressed sound. During the recent old ages the application of MP3 sound codec has exploded. Typically MP3 files are played back utilizing package ( CPU or DSP ) , but recent tendencies have since informant the outgrowth of portable device, such as nomadic phones and MP3 participants. While DSP architecture is the most efficient for running MP3 participant, the challenges of FPGA execution of MP3 decrypting are less understood.
Field Programmable Gate Array, merely known as FPGA, is one type of incorporate circuit that is consumer-programmable, therefore it is called “field programmable” . This incorporate circuit uses hardware descriptive linguistic communication ( HDL ) to configure. Nowadays, FPGA has since advanced into a high degree of efficiency during the past decennary. It has since become the major HP in different types of application, since it can be employed as standalone System on Chip ( SoC ) or powerful gas pedals in multi-chip system.
The mark of the undertaking is to implement the MP3 decrypting nucleus by using the FPGA belongingss. While utilizing the bing package codification to run the decipherer in package, efforts has been done to run the decipherer in hardware, which will go the chief way in this undertaking. Then, comparing the public presentation of these two methods will besides be the focal point of the undertaking.

Aim

The aim of this undertakings are:

To plan the MP3 decipherer hardware based and can be implemented in portable based design
To measure the efficiency of the hardware based decipherer comparison to the common package based decipherer

Problem Statement

Most of the MP3 decryption designs are of in package. However, the hardware importance of the decryption design has since taken the popularity today. Therefore, several efforts have been taken to make the to the full hardware architecture of the decryption nucleus. This paper will measure the efficiency of the hardware decipherer as per package decipherer and to look into the advantages of both methods.

Scope of the Undertaking

The range of the undertaking includes combination of several elements such as hardware, package and electronic parts. Below are the Scopess for the undertaking.

Uses Verilog HDL linguistic communication as its chief footing for programming
Explore the application of Verilog utilizing Altera DE2 Board
Include package programming such as C and C++
Implement the application ( partial ) utilizing downloaded package for package execution ( Quartus II 9.1, Nios II 9.1 )

Chapter 2
LITERATURE REVIEW
In 1988, Hiroshi Yasuda ( Nippon Telegraph and Telephone ) and Leonardo Chiariglione had initiated the working group Traveling Pictures Experts Group ( MPEG ) to put the criterions for audio and video compaction and transmittal. The group, formed by International Organisation for Standardisation ( ISO ) and International Electrotechnical Commission ( IEC ) , has since developed into an organisation joined by members from assorted industries, universities and research establishments. One of the criterions that have created is the MPEG-1 Layer 3, or good known as MP3. MP3 is the standard format used for digital audio compaction, in which the design have 12:1 compaction ratio, from 1.4Mbps 128kbps bitrate for compact phonograph record ( Cadmium ) music.

Related Studies and Previous Work

It is known that MP3 decrypting procedure is a hard procedure, but several research workers and industrialist have attempted to plan the decipherer for this specific format. For case, Faltmanet Al.( 2003 ) have stated that the designing of MP3 decrypting in portable and stand-alone participants have gained in popularity. In the study, Faltmanet Al.( 2003 ) besides stated the importance in the public presentation of these hardware MP3 decrypting based on the clock rhythms and power use. It besides includes an effort to to make an MP3 decipherer in hardware, by utilizing Xilinx FPGA board. Thuonget Al.( 2005 ) have proposed the architecture of the MP3 decryption nucleus, in which the subcores of the architecture can be separately designed, coded and tested easy. However, the design of the nucleus is coded utilizing VHDL, the older version of RTL linguistic communication.
Ko and Nicolici ( 2007 ) have tested the execution of the nucleus utilizing Altera DE2 board and Xilinx multimedia board. It besides has consequences including the figure of logic elements, reversals, memories and multipliers involved. Bhargav and Yang ( 2008 ) have introduced the use of Linux-run interface on the decryption nucleus. Their research has besides opened the possibilities of animating the popular piece of consumer engineering utilizing bing hardware available in the lab. Still, the design utilizes both hardware and package constituent in their design architecture. It has few general lags due to system clock and debugging procedure.
Singhet Al.( 2008 ) have proposed that the demand of hand-held participants and multimedia in nomadic phone have raised a demand for a dedicated hardware to decrypt the file formats with low power ingestion and faster acceleration. Papakonstantinouet Al.( 2008 ) have researched instance survey on the execution of drifting point math in decipherer execution to accomplish existent clip and faster decrypting procedure. In the instance survey, the writers introduce floating-point ( FP ) unit in their architecture to measure the operation velocity ; therefore naming it the FP execution of MP3 decryption.
In the latest research by Moslehpouret Al.( 2013 ) , the undertaking uses NIOS II system, which is a portion of package device, to read files and produces end product from the decrypting procedure. By utilizing unafraid digital ( SD ) card as input devices, the system uses Altera DE2 board but synthesize different file format: moving ridge files, or.wav extension files. Even so, the exposure of the study have shown that running the decipherer is possible, peculiarly because of package characteristics use Altera SOPC builder in Altera Quartus 9.1 environment, in which the platform is largely used in third instruction degree.
Some of the old work did even make the architectural design of MP3 decipherer, utilizing a VLSI cell-based attack. Tsaiet Al.( 2004 ) have proposed the specific architectural construction of MP3 decipherer in which it achieves a high throughput with a decreased memory demand and hardware complexness. Meanwhile, Kalpanaet Al.( 2012 ) have tried to implement the algorithm on the decreased direction set computer science ( RISC ) based ARM processor, which is far more advanced, proficient wised.
All of the old work did hold its important characteristics in edifice MP3 decryption nucleus, either in hardware or package. However, the execution of MP3 decrypting IP nucleus, which uses Verilog HDL as its hardware linguistic communication, as implementing it to the full hardware based is non good discovered. Therefore, the focal point is the study is to undertake the design of MP3 decrypting nucleus, on the surface at least.

Introduction to the MP3 Decoding Core

Harmonizing to Kalpanaet Al.( 2012 ) , all MP3 files are divided into fragments called frames. Each frames shops 1152 samples, enduring for 26ms, which the frame rate is about 38 frame per second ( Federal Protective Service ) . The first measure to decrypt MP3 file format is by happening the start of the frame, which is called synchronism procedure, or else called initial reading.

Synchroscope

Before decryption, the start of the frame must be found. If the frame is interrupted, we can non happen the exact place of the following frame ( Thuonget Al., 2007 ) . The construction of the frame consists of 5 parts ; heading, cyclic redundancy cheque ( CRC ) , side information, chief informations and accessory informations.

Heading

CRC

Side Information

Main informations

Ancillary Data

Figure 2.1The MP3 bitstream format
The inside informations about the frame heading is as follows:

Frame Header

It is a 32-bit long and has description of the frame, together with the synchronism word to separate the get downing portion of the bitstream

CRC

Use to look into if there is any transmittal mistake for the most sensitive informations. The CRC will merely exists when the protection spot in the heading is set.

Side Information

Includes the of import information needed to decrypt the chief information. This depends on the channel manner. For individual channel, 136 spots are allocated, while for double channel, 256 spot allocated ( this is tantamount to 17 bytes in individual channel, 32 bytes in dual-channel )

Main Data

The chief informations portion consists of the frames that includes scalefactors, Huffman coded spots and accessory informations

Ancillary Data

This information can keep user-defined information. This frame country can keep optional informations such as vocal name or song information.

Huffman Decoding

This subdivision contains one of the most of import undertaking in MP3 decryption. The undertaking of Huffman decrypting is to transform and mapping the information into scalefactors and symbols stand foring the 576 original frequence lines for each granule. These frequence line is divided into three divider ;Big-values,Count1andRzero.

Big-values

Count1

Rzero

Figure 2.2The three parts of frequence line
Detailss on the Huffman codification divider are as follows:

Big-values

Represents the lowest frequence lines and are coded with the highest preciseness, scaled from values between -15 to 15. When the decipherer finds the value 15, it assumes that the higher preciseness is needed. This can be done by utilizing the value 15 as an flight codification, so reads extra spots from the imput watercourse. The figure specified in the Huffman tabular array are called linbits.

Count1

Represent the higher frequence lines ; non necessitate the higher preciseness scaled value. Ranging from -1 to 1.

Rzero

Represent the highest frequence lines, and non portion of the bitstream. It contains the the frequence lines that are removed by the encoder. These values are filled with nothing by the decipherer.

Requantiser

The symbols generated from Huffman decrypting is so reconstructed into the original frequence line by utilizing the scalefactors provided in the side information of the frame. The low frequence scalefactor set contains less values than the high frequence.
The descaling equation for both short blocks and long blocks are defined as
Short blocks:

Long blocks:

The denoted scalefactorsscalefactor_sandscalefactor_lused by requantiser are provided by Huffman decipherer. Parametersglobal_gain,subblock_gainandpreflagcan be found in the frames provided by the Synchroniser block. The notaiondefines end product from the Requantser block, whileis the Huffman decoded value at indexI.

Reordering

This block merely has one undertaking: it reorders the frequence lines within a granule. When the short block is decoded, a short window will be used. The end product is so sorted into subbands, so on frequences and at last by Windowss to increase the efficiency of Huffman coding.

Figure 2.3The reordering procedure ( the darker coloring material represents higher frequences )

Antialiasing

Antialiasing is the procedure where its map is to cut down the inevitable assumed name effects because of the use of non-ideal bandpass filtering. The alias Reconstruction is based on the butterfly computation, dwelling of eight butterfly computation for each subband.

Figure 2.4The antialias butterfly

Inverse Modified Discrete Cosine Transform

Inverse Modified Discrete Cosine Transform, known as IMDCT, reproduce clip samples from the frequence lines, together with synthesis polyphase filterbank. The clip samples can be obtained from the frequence lines by utilizing the undermentioned equation.

The IMDCT operation flow begins by taking 18 input frequence lines and generates 36 polyphase filter subband samples. The samples so multiplied with with a 36-point window before passed into following decryption procedure. Windowing is the procedure of multiplying and overlapping add-on operation of IMDCT’s end product with the sine window coefficient. Based on the length of each window, four types of block is used ; they arestart,halt,shortandlong. The determination of block type is based on the analysis of the psychoacoustic theoretical account.

Figure 2.5Types of window sequences in a subband
However, bring forthing 36 samples from 18 input means that there are merely 18 samples are alone, therefore the IMDCT method uses a 50 % convergence. In this instance, the 36 end product samples is so divided into 2 groups, low group and high group, which has 18 samples each. The overlapping procedure is so carried out by adding values from the higher group, old frame with the lower group, matching frame. Then, the frequence inversion is so taken topographic point to accomplish right stage difference. This was done by multiplying every uneven subband with ( -1 ) .

Figure 2.6The IMDCT operation flow

Synthesis Polyphase Filterbank

This block is the last measure in decrypting procedure. It converts all 32 subbands to bring forth 32 Pulse Code Modulation ( PCM ) samples at a clip The filterbank exploits aliasing and windowing to travel the subbands back into their frequence sphere. This block is divided into two parts ; Modified Discrete Cosine Transform ( MDCT ) and windowing.

Modified Discrete Cosine Transform

Each clip frame of the subband samples are ordered so that the first 32 values are the first sub-sample from each subband, and so forth. The MDCT processes 32 values at a clip by utilizing the equation:

where
The end point end product values,is so stored in the barrel shifter.

Windowing

The windowing procedure tallies by multiplying the valuesfrom the barrel shifter with the window map. This window map is specified in the ISO criterion. The PCM generated are so computed for each loop. The MDCT and windowing together run 18 times for each granule, bring forthing 576 PCM samples ( 27ms at 44.1kHz ) .
Chapter 3
RESEARCH METHODOLOGY

Introduction

This chapter discusses the well planned attack taken during the project’s timeline to guarantee that the undertaking is good organized and run expeditiously. The methodological analysis is represented into a flow chart for easiness of apprehension.

Ocular Representation of Research Methodology

The designate work flow for the undertaking is shown below, in Figure 3.1.

Figure 3.1The undertaking work flow
The undertaking begins by researching any old plants related to the MP3 decryption and FPGA-based architecture execution. Besides that, several resources on hardware descriptive linguistic communication and package programming tutorial have besides looked at. The procedure involved in constructing the nucleus is studied and briefly elaborated to give excess cognition in order to carry through the research. The importance and intent of the undertaking is besides discussed in the first phase.
The hardware used for proving and implementing the undertaking is Altera DE2 Educational Development Board.

Figure 3.2The Altera DE2 board ( beginning: hypertext transfer protocol: //www.terasic.com.tw/ )

Altera DE2 Board

The Altera DE2 board provides everything needed to develop many advanced digital designs utilizing Altera Cyclone II device, with utilizing application package Altera Quartus II. This development board is the first measure to present and larn basic FPGA devices easy, since it is accessible in the lab. It is suited for a broad scope of exercisings in classs on digital logic and computing machine organisation, from simple undertakings that illustrate cardinal constructs to progress designs.

Altera Quartus II

Figure 3.3The Quartus II work bench environment
Altera Quartus II is a package tool produced by Altera for analysis and synthesis of HDL designs, which enables the user to roll up their designs, execute clocking analysis, analyze RTL diagrams, imitate a design ‘s reaction and configure the mark device with the coder.

NIOS II

Figure 3.4The NIOS II work bench environment
Nios II is the most widely used soft processor in the FPGA industry. Nios II incorporates many sweetenings over the original predecessor, Nios architecture, doing it more suited for a wider scope of embedded computer science applications, from DSP to system-control. The development for Nios II consists of two separate stairss: hardware coevals, and package creative activity.

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